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Fixed Sequence Traffic Light Controller in VHDL

This is the second homework for the course of Programmable Logic Devices in the 2021-2022 Spring semester of West Pomeranian University of Technology.

In the homework, we're asked to create a controller device for such a crossroad, prepare its state diagram and code the FPGA with using VHDL. One should notice that in the assignment's instructions document, we have no information about the light status of the pedestrians if the vehicle lights in the state of green and yellow is on. I made a decision to make pedestrians stop (red) in that states, since it is much more safer to do it.

Figure (1): Representation of the Crossroad

This design does not care about the traffic itself. Therefore, it is known as fixed-sequence (which means always with the same delay translation) traffic lights system.

Task 1. Creating a State Table

There are eight different state that we can write for this example. After the state S8, the mechanism will move to the beginning, to S1.

Number State Vehicle V1 Pedestrian P1 Vehicle V2 Pedestrian P2 Description
1 S1 100 010 100 010 All are read light.
2 S2 110 010 100 010 Vehicles on V1 starts to go.
3 S3 001 001 100 010 Vehicles on V1 goes, Pedestrains on P1 goes.
4 S4 011 010 100 010 Vehicles on V1 start to stop, Pedestrains on P1 stops.
5 S5 100 010 100 010 All are read light.
6 S6 100 010 110 010 Vehicles on V2 starts to go.
7 S7 100 010 001 001 Vehicles on V2 goes, Pedestrains on P2 goes.
8 S8 100 010 011 010 Vehicles on V2 start to stop, Pedestrains on P2 stops.

Task 2. Represent the States with a Diagram

In the second figure, you can find the state diagram for our traffic light design. Notice that changing between states only depends on the timer, which is shown as #LIGHT_MS concept. In the assignment paper, it is said to us that #RED_MS = #YELLOW_MS = #GREEN_MS = 1000 ms.

Figure (2): State Diagram for Our Project

Task 3. Implement it using the VHDL

I'll create a controller which has the inputs and the outputs as shown in Figure (3).

Figure (3): The Controller RTL Scheme