Building Own Computer with Nand2Tetris: Project III

After a long break, I was able to find time for this course I took from Coursera and I finished the project of the third week. I should point out that I was in a bit of a rush to design the Program Counter and got help from the discussion forums.

This week's project is totally about memories.

I hope to finish this course soon. In addition, I will add two homework projects that I will do in my FPGA VHDL course, which I took at school in parallel with the course, to my blog soon.

Bit

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Bit.hdl

/**
 * 1-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 *                 else out does not change (out[t+1] = out[t])
 */

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    Mux (a=outDFF, b=in, sel=load, out=wire1);
    DFF (in=wire1, out=out, out=outDFF);
}

Register

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Register.hdl

/**
 * 16-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 * else out does not change
 */

CHIP Register {
    IN in[16], load;
    OUT out[16];

    PARTS:
	Bit (in=in[0], load=load, out=out[0]);
	Bit (in=in[1], load=load, out=out[1]);
	Bit (in=in[2], load=load, out=out[2]);
	Bit (in=in[3], load=load, out=out[3]);
	Bit (in=in[4], load=load, out=out[4]);
	Bit (in=in[5], load=load, out=out[5]);
	Bit (in=in[6], load=load, out=out[6]);
	Bit (in=in[7], load=load, out=out[7]);
	Bit (in=in[8], load=load, out=out[8]);
	Bit (in=in[9], load=load, out=out[9]);
	Bit (in=in[10], load=load, out=out[10]);
	Bit (in=in[11], load=load, out=out[11]);
	Bit (in=in[12], load=load, out=out[12]);
	Bit (in=in[13], load=load, out=out[13]);
	Bit (in=in[14], load=load, out=out[14]);
	Bit (in=in[15], load=load, out=out[15]);
}

RAM8

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM8.hdl

/**
 * Memory of 8 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
    	DMux8Way (in=load, sel=address, a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
	Register (in=in, load=load0, out=out0);
	Register (in=in, load=load1, out=out1);
	Register (in=in, load=load2, out=out2);
	Register (in=in, load=load3, out=out3);
	Register (in=in, load=load4, out=out4);
	Register (in=in, load=load5, out=out5);
	Register (in=in, load=load6, out=out6);
	Register (in=in, load=load7, out=out7);
	Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address, out=out);

}

RAM64

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl

/**
 * Memory of 64 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];

    PARTS:
    	DMux8Way (in=load, sel=address[0..2],
				a=loadRAM0,
				b=loadRAM1,
				c=loadRAM2,
				d=loadRAM3,
				e=loadRAM4,
				f=loadRAM5,
				g=loadRAM6,
				h=loadRAM7
	);

    	RAM8 (in=in, load=loadRAM0, address=address[3..5], out=outRAM0);
	RAM8 (in=in, load=loadRAM1, address=address[3..5], out=outRAM1);
	RAM8 (in=in, load=loadRAM2, address=address[3..5], out=outRAM2);
	RAM8 (in=in, load=loadRAM3, address=address[3..5], out=outRAM3);
	RAM8 (in=in, load=loadRAM4, address=address[3..5], out=outRAM4);
	RAM8 (in=in, load=loadRAM5, address=address[3..5], out=outRAM5);
	RAM8 (in=in, load=loadRAM6, address=address[3..5], out=outRAM6);
	RAM8 (in=in, load=loadRAM7, address=address[3..5], out=outRAM7);

	Mux8Way16 (sel=address[0..2], out=out,
				a=outRAM0,
				b=outRAM1,
				c=outRAM2,
				d=outRAM3,
				e=outRAM4,
				f=outRAM5,
				g=outRAM6,
				h=outRAM7);
}

RAM512

// This file is part of the materials accompanying the book 
// "The Elements of Computing Systems" by Nisan and Schocken, 
// MIT Press. Book site: www.idc.ac.il/tecs
// File name: projects/03/b/RAM512.hdl

/**
 * Memory of 512 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];

    PARTS:
	    DMux8Way (in=load, sel=address[0..2],
                               a=loadRAM0,
                               b=loadRAM1,
                               c=loadRAM2,
                               d=loadRAM3,
                               e=loadRAM4,
                               f=loadRAM5,
                               g=loadRAM6,
                               h=loadRAM7
        );

        RAM64 (in=in, load=loadRAM0, address=address[3..8], out=outRAM0);
        RAM64 (in=in, load=loadRAM1, address=address[3..8], out=outRAM1);
        RAM64 (in=in, load=loadRAM2, address=address[3..8], out=outRAM2);
        RAM64 (in=in, load=loadRAM3, address=address[3..8], out=outRAM3);
        RAM64 (in=in, load=loadRAM4, address=address[3..8], out=outRAM4);
        RAM64 (in=in, load=loadRAM5, address=address[3..8], out=outRAM5);
        RAM64 (in=in, load=loadRAM6, address=address[3..8], out=outRAM6);
        RAM64 (in=in, load=loadRAM7, address=address[3..8], out=outRAM7);

        Mux8Way16 (sel=address[0..2], out=out,
                                      a=outRAM0,
                                      b=outRAM1,
                                      c=outRAM2,
                                      d=outRAM3,
                                      e=outRAM4,
                                      f=outRAM5,
                                      g=outRAM6,
                                      h=outRAM7);
}

RAM4K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
            DMux8Way (in=load, sel=address[0..2],
                               a=loadRAM0,
                               b=loadRAM1,
                               c=loadRAM2,
                               d=loadRAM3,
                               e=loadRAM4,
                               f=loadRAM5,
                               g=loadRAM6,
                               h=loadRAM7
        );

        RAM512 (in=in, load=loadRAM0, address=address[3..11], out=outRAM0);
        RAM512 (in=in, load=loadRAM1, address=address[3..11], out=outRAM1);
        RAM512 (in=in, load=loadRAM2, address=address[3..11], out=outRAM2);
        RAM512 (in=in, load=loadRAM3, address=address[3..11], out=outRAM3);
        RAM512 (in=in, load=loadRAM4, address=address[3..11], out=outRAM4);
        RAM512 (in=in, load=loadRAM5, address=address[3..11], out=outRAM5);
        RAM512 (in=in, load=loadRAM6, address=address[3..11], out=outRAM6);
        RAM512 (in=in, load=loadRAM7, address=address[3..11], out=outRAM7);

        Mux8Way16 (sel=address[0..2], out=out,
                                      a=outRAM0,
                                      b=outRAM1,
                                      c=outRAM2,
                                      d=outRAM3,
                                      e=outRAM4,
                                      f=outRAM5,
                                      g=outRAM6,
                                      h=outRAM7);
}

RAM16K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl

/**
 * Memory of 16K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];

    PARTS:
            DMux4Way (in=load, sel=address[0..1],
                               a=loadRAM0,
                               b=loadRAM1,
                               c=loadRAM2,
                               d=loadRAM3);

        RAM4K (in=in, load=loadRAM0, address=address[2..13], out=outRAM0);
        RAM4K (in=in, load=loadRAM1, address=address[2..13], out=outRAM1);
        RAM4K (in=in, load=loadRAM2, address=address[2..13], out=outRAM2);
        RAM4K (in=in, load=loadRAM3, address=address[2..13], out=outRAM3);

        Mux4Way16 (sel=address[0..1], out=out,
                                      a=outRAM0,
                                      b=outRAM1,
                                      c=outRAM2,
                                      d=outRAM3);
}

Program Counter (PC)

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.hdl

/**
 * A 16-bit counter with load and reset control bits.
 * if      (reset[t] == 1) out[t+1] = 0
 * else if (load[t] == 1)  out[t+1] = in[t]
 * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
 * else                    out[t+1] = out[t]
 */

CHIP PC {
    IN in[16],load,inc,reset;
    OUT out[16];

    PARTS:
    	Register (in=outSystem, out=outRegister, out=out, load=true);
	Inc16 (in=outRegister, out=outIncrementor);
	Mux16 (a=outRegister, b=outIncrementor, sel=inc, out=MuxIncOut);
	Mux16 (a=MuxIncOut, b=in, sel=load, out=MuxLoadOut);
	Mux16 (a=MuxLoadOut, b=false, sel=reset, out=outSystem);
}