Building Own Computer with Nand2Tetris: Project I

I should create every logic gate from using only NAND or previously built gates. In the course, HDL language is its own type – but similar to VHDL, the instructor says.

AND Gate

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/And.hdl

/**
 * And gate: 
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    Nand (a=a, b=b, out=notAB);
    Nand(a=notAB, b=notAB, out=out);
}

HDL representation of AND gate using NANDs.

AND

Logism Evolution circuit for AND gate using NAND.

AND.circ

4 KB

NOT Gate

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Not.hdl

/**
 * Not gate:
 * out = not in
 */

CHIP Not {
    IN in;
    OUT out;

    PARTS:
    Nand (a=in, b=in, out=out);
}

HDL representation of NOT gate using NANDs.

NOT

Logism Evolution circuit for NOT gate using NAND.

NOT.circ

2 KB

OR Gate

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Or.hdl

 /**
 * Or gate:
 * out = 1 if (a == 1 or b == 1)
 *       0 otherwise
 */

CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    Not (in=a, out=notA);
    Not (in=b, out=notB);
    Nand (a=notA, b=notB, out=out);
}

HDL representation of OR gate using NAND and NOTs.

Logism Evolution circuit for OR gate using NAND and NOT.

OR.circ

3 KB

XOR Gate

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Xor.hdl

/**
 * Exclusive-or gate:
 * out = not (a == b)
 */

CHIP Xor {
    IN a, b;
    OUT out;

    PARTS:
    Not (in=a, out=notA);
    Not (in=b, out=notB);
    And (a=a, b=notB, out=o1);
    And (a=notA, b=b, out=o2);
    Or (a=o1, b=o2, out=out);
}

HDL representation of XOR gate using NOTs, ANDs, and OR.

XOR

Logism Evolution circuit for XOR gate using NOT, AND, and OR.

XOR.circ

4 KB

MUX (Multiplexer) Gate

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Mux.hdl

/** 
 * Multiplexor:
 * out = a if sel == 0
 *       b otherwise
 */

CHIP Mux {
    IN a, b, sel;
    OUT out;

    PARTS:
    Not (in=sel, out=notSel);
    And (a=a, b=notSel, out=o1);
    And (a=sel, b=b, out=o2);
    Or (a=o1, b=o2, out=out);
 }

HDL representation of MUX gate using NOT, ANDs, and OR.

MUX

Logism Evolution circuit for MUX gate using NOT, AND, and OR.

MUX.circ

4 KB

DMux (Demultiplexer) Gate

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/DMux.hdl

/**
 * Demultiplexor:
 * {a, b} = {in, 0} if sel == 0
 *          {0, in} if sel == 1
 */

CHIP DMux {
    IN in, sel;
    OUT a, b;

    PARTS:
    Not (in=sel, out=notSel);
    And (a=notSel, b=in, out=a);
    And (a=in, b=sel, out=b);
}

HDL representation of DMUX gate using NOT, ANDs.

DMUX

Logism Evolution circuit for DMUX gate using NOT and ANDs.

DMUX.circ

3 KB

16-bit Gates

Since that all the logic behind the construction of one-bit and sixteen-bit gates are the same, but the number of gate huge, I won't put the schematics and Logism circuit files in this section.

Not16

CHIP Not16 {
    IN in[16];
    OUT out[16];

    PARTS:
    Not (in=in[0], out=out[0]);
    Not (in=in[1], out=out[1]);
    Not (in=in[2], out=out[2]);
    Not (in=in[3], out=out[3]);
    Not (in=in[4], out=out[4]);
    Not (in=in[5], out=out[5]);
    Not (in=in[6], out=out[6]);
    Not (in=in[7], out=out[7]);
    Not (in=in[8], out=out[8]);
    Not (in=in[9], out=out[9]);
    Not (in=in[10], out=out[10]);
    Not (in=in[11], out=out[11]);
    Not (in=in[12], out=out[12]);
    Not (in=in[13], out=out[13]);
    Not (in=in[14], out=out[14]);
    Not (in=in[15], out=out[15]);
}

And16

CHIP And16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    And (a=a[0], b=b[0], out=out[0]);
    And (a=a[1], b=b[1], out=out[1]);
    And (a=a[2], b=b[2], out=out[2]);
    And (a=a[3], b=b[3], out=out[3]);
    And (a=a[4], b=b[4], out=out[4]);
    And (a=a[5], b=b[5], out=out[5]);
    And (a=a[6], b=b[6], out=out[6]);
    And (a=a[7], b=b[7], out=out[7]);
    And (a=a[8], b=b[8], out=out[8]);
    And (a=a[9], b=b[9], out=out[9]);
    And (a=a[10], b=b[10], out=out[10]);
    And (a=a[11], b=b[11], out=out[11]);
    And (a=a[12], b=b[12], out=out[12]);
    And (a=a[13], b=b[13], out=out[13]);
    And (a=a[14], b=b[14], out=out[14]);
    And (a=a[15], b=b[15], out=out[15]);
}

Or16

CHIP Or16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Or (a=a[0], b=b[0], out=out[0]);
    Or (a=a[1], b=b[1], out=out[1]);
    Or (a=a[2], b=b[2], out=out[2]);
    Or (a=a[3], b=b[3], out=out[3]);
    Or (a=a[4], b=b[4], out=out[4]);
    Or (a=a[5], b=b[5], out=out[5]);
    Or (a=a[6], b=b[6], out=out[6]);
    Or (a=a[7], b=b[7], out=out[7]);
    Or (a=a[8], b=b[8], out=out[8]);
    Or (a=a[9], b=b[9], out=out[9]);
    Or (a=a[10], b=b[10], out=out[10]);
    Or (a=a[11], b=b[11], out=out[11]);
    Or (a=a[12], b=b[12], out=out[12]);
    Or (a=a[13], b=b[13], out=out[13]);
    Or (a=a[14], b=b[14], out=out[14]);
    Or (a=a[15], b=b[15], out=out[15]);
}

Mux16

CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    Mux (a=a[0], b=b[0], sel=sel, out=out[0]);
    Mux (a=a[1], b=b[1], sel=sel, out=out[1]);
    Mux (a=a[2], b=b[2], sel=sel, out=out[2]);
    Mux (a=a[3], b=b[3], sel=sel, out=out[3]);
    Mux (a=a[4], b=b[4], sel=sel, out=out[4]);
    Mux (a=a[5], b=b[5], sel=sel, out=out[5]);
    Mux (a=a[6], b=b[6], sel=sel, out=out[6]);
    Mux (a=a[7], b=b[7], sel=sel, out=out[7]);
    Mux (a=a[8], b=b[8], sel=sel, out=out[8]);
    Mux (a=a[9], b=b[9], sel=sel, out=out[9]);
    Mux (a=a[10], b=b[10], sel=sel, out=out[10]);
    Mux (a=a[11], b=b[11], sel=sel, out=out[11]);
    Mux (a=a[12], b=b[12], sel=sel, out=out[12]);
    Mux (a=a[13], b=b[13], sel=sel, out=out[13]);
    Mux (a=a[14], b=b[14], sel=sel, out=out[14]);
    Mux (a=a[15], b=b[15], sel=sel, out=out[15]);
}

Multi-way Variants

In this section, we're going to construct Mux and DMux gates with more than two input channels.

Or8Way

/**
 * 8-way Or: 
 * out = (in[0] or in[1] or ... or in[7])
 */

CHIP Or8Way {
    IN in[8];
    OUT out;

    PARTS:
    Or (a=in[0], b=in[1], out=out1);
    Or (a=out1, b=in[2], out=out2);
    Or (a=out2, b=in[3], out=out3);
    Or (a=out3, b=in[4], out=out4);
    Or (a=out4, b=in[5], out=out5);
    Or (a=out5, b=in[6], out=out6);
    Or (a=out6, b=in[7], out=out);
}

It is just serial OR gates.

Mux4Way16

/**
 * 4-way 16-bit multiplexor:
 * out = a if sel == 00
 *       b if sel == 01
 *       c if sel == 10
 *       d if sel == 11
 */

CHIP Mux4Way16 {
   IN a[16], b[16], c[16], d[16], sel[2];
   OUT out[16];

   PARTS:
   Not (in=sel[1], out=notSel0);
   And (a=notSel0, b=sel[0], out=muxSel1);
   And (a=sel[1], b=sel[0], out=muxSel2);
   Mux16 (a=a, b=b, sel=muxSel1, out=out1);
   Mux16 (a=c, b=d, sel=muxSel2, out=out2);
   Mux16 (a=out1, b=out2, sel=sel[1], out=out);
}

Please notice that we have used sel[1] for first bit, and sel[0] for second bit of selection input.

Mux8Way16

/**
 * 8-way 16-bit multiplexor:
 * out = a if sel == 000
 *       b if sel == 001
 *       etc.
 *       h if sel == 111
 */

CHIP Mux8Way16 {
    IN a[16], b[16], c[16], d[16],
       e[16], f[16], g[16], h[16],
       sel[3];
    OUT out[16];

    PARTS:
    Mux4Way16 (a=a, b=b, c=c, d=d, sel=sel[0..1], out=MuxOut1);
    Mux4Way16 (a=e, b=f, c=g, d=h, sel=sel[0..1], out=MuxOut2);
    Mux16 (a=MuxOut1, b=MuxOut2, sel=sel[2], out=out);
}

DMux4Way

/**
 * 4-way demultiplexor:
 * {a, b, c, d} = {in, 0, 0, 0} if sel == 00
 *                {0, in, 0, 0} if sel == 01
 *                {0, 0, in, 0} if sel == 10
 *                {0, 0, 0, in} if sel == 11
 */

CHIP DMux4Way {
    IN in, sel[2];
    OUT a, b, c, d;

    PARTS:
    DMux (in=in, sel=sel[1], a=O1, b=O2);
    DMux (in=O1, sel=sel[0], a=a, b=b);
    DMux (in=O2, sel=sel[0], a=c, b=d);
}

DMux8Way

/**
 * 8-way demultiplexor:
 * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
 *                            {0, in, 0, 0, 0, 0, 0, 0} if sel == 001
 *                            etc.
 *                            {0, 0, 0, 0, 0, 0, 0, in} if sel == 111
 */

CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;

    PARTS:
    DMux (in=in, sel=sel[2], a=O1, b=O2);
    DMux4Way (in=O1, sel=sel[0..1], a=a, b=b, c=c, d=d);
    DMux4Way (in=O2, sel=sel[0..1], a=e, b=f, c=g, d=h);
}